In order to respond to a demand for high densification of printed circuit boards along with high-density mounting, a multilayer printed circuit board having plural printed circuit boards laminated one on another has been developed. In the case of such a multilayer printed circuit board, micro through-holes having a diameter of about at most 100 μm so called via holes are formed on an insulating layer made of a resin, and the inside of the through-holes are plated so as to electrically connect conductive layers each other between printed circuit boards which are laminated one above the other.
As the method for easily forming such through-holes, Patent Documents 1 and 2 disclose a method of emitting laser light to an insulating layer through a mask in which plural holes are formed. According to such a method, since plural through-holes can be simultaneously formed on an insulating layer made of a resin, it is considered that many through-holes (via holes) can be easily formed.
Further, in order to respond to a demand to make IC chips small in size and thin, the wafer level package (WLP) technique is often utilized in recent years. The WLP technique is a technique such that a wafer surface on which IC is formed is subjected to re-wiring, solder bump printing, resin sealing or the like required for semiconductor packages, and then the wafer is die-cut into individual wafers, whereby the package size of the wafer is reduced to the same level of IC chips. In WLP, silicon wafers sealed with a resin are usually die-cut into individual wafers. However, in recent years, silicon wafers bonded to glass by anode joint or the like are used from the viewpoint of reliability. In a case where glass used in WLP is used for through-holes or a sensor for electrodes, through-holes for informing information of air (temperature, pressure, air flow, etc.) directly to chips are additionally formed on the glass.
In addition, since the demand for making semiconductor devices small in size, fast and low energy consumptive is further increasing, the development of the three dimensional SiP technique is in progress in which the system-in-package (SiP) technique to put a system comprising plural LSI in one package and the three dimensional mounting technique are combined. In such a case, wiring bonding cannot be applied to micro pitches, and a connection substrate so called interposer employing through-hole electrodes is required.